The present invention relates in general to computer aided design tools, and in particular to a netlisting tool that provides hierarchical netlists using a method of expression promotion.
The process of computer aided design (CAD) includes an initial step of creating a schematic diagram of the circuit to be simulated. It is to be understood that in this description, the circuit refers to transistor level as well as gate level circuits. The circuit schematic diagram is a symbolic representation of the electronic circuit and is typically hierarchical in design. Upon entering the schematic into the computer, including circuit component parameters, the computer performs what is referred to as schematic capture or netlisting. Netlisting usually encompasses the traversal of a hierarchical design database to generate a textual or binary representation of the design. The netlist is subsequently read by a simulator that performs circuit simulation.
To minimize the size of the netlist, it is desirable to maintain the circuit hierarchy structure in the textual or binary representation. To facilitate hierarchical representation, many CAD tools available today provide for parameter passing. Parameter passing allows the use of arguments in defining sub-circuits or "macros," typically as property values for individual components in the macro. Once defined, the same macro may be used in several different instances at the same or different levels of the circuit hierarchy. During the netlist read-in phase, the hierarchical netlist is flattened such that each call to a macro results in a unique set of components. Any component whose property values were defined by macro arguments will have those values reflected as the property values of the unique, flattened component.
Since this methodology requires the flattening of the hierarchy, such parameter passing often has been limited to passing of simple numeric parameters as arguments to macro calls. More advanced CAD tools now allow the user to define circuit component property values with algebraic expressions. These algebraic expressions may contain variables that are defined at different levels of hierarchy. For these tools, maintaining the hierarchy in the representation gives rise to several practical problems. To process algebraic expressions, the tool would have to be capable of fully evaluating algebraic expressions upon flattening the netlist to generate a numeric value for each component property. Typical CAD tools, however, provide simulators that can only evaluate the most fundamental forms of expressions. More complex expressions, with potential calls to arbitrary mathematical functions or user-defined functions, cannot be evaluated unless the simulator has these functions defined in the evaluation environment. For a truly general case, this is simply not feasible.
An alternative approach requires that the netlisting environment contain all function definitions such that algebraic expressions can be evaluated upon netlist creation. Using this approach, the netlist provided to the simulator has only numeric component property values and no further evaluation is necessary. This, however, places the responsibility on the tool that does the parameter substitutions and expression evaluation (i.e., netlister) to also insure that a unique set of components be created. The netlister is therefore required to textually duplicate a macro definition each time the macro is referenced with a different set of calling parameters. For highly parametric designs, this flattening process leads to unduly large textual or binary representations, rendering the approach impractical for large digital designs.
There is therefore a need for a netlisting tool that provides for passing of design parameters into a given level of hierarchy for use in algebraic expressions defining circuit component properties.